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Oxidation, Ion-Implantation and RTP/Furnace Processing

Paper Type: Free Essay Subject: Mechanics
Wordcount: 3968 words Published: 23rd Sep 2019

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MCEE201/601 – Report#1

Oxidation, Ion-Implantation and RTP/Furnace Processing



The Lab course’s goal is to perform how to design, fabricate and characterize a simple P-type-metal oxide-semiconductor (PMOS) device. In this lab report, details about the oxidation, ion implantation and rapid thermal processing (RTP), which are some of main processes of PMOS fabrication procedure, is reported. Three specific wafers, but similar at initiation (lightly doped N-type Silicon) were marked C1, C2 and C3 to be used in order to monitor our different process steps. The process began with RCA cleaning followed by wet oxidization and mask pattering in order to prepare wafers for ion-implantation. The C1 wafer was step-etched for upcoming evaluation. Ion-implantation was performed on all the three wafers with Boron as a dopant. Afterwards, C1 and C3 wafers went through Rapid Thermal Annealing to activate bombarded dopant. Sheet resistance (Rs) measurement via 4-point probe technique was executed on C1 wafer to evaluate the minimum oxide thickness of ion-implantation mask based on Rs. In order to increase the junction depth, furnace thermal processing was done on C2 wafer. Steam oxide was grown and etched on C2 wafer as well. Groove and Stain technique was performed on C2 wafer for junction depth (Xj) measurements. Athena software was used for better understanding and also to make some comparison between measured and simulated values such as dopant profile, minimum mask oxide thickness, and junction depth and sheet resistance.

1. Introduction


Microfabrication course is about the theory behinds common methods and techniques for semiconductor device fabrication with focus on transistors. In Lab session, all these methods practically shown by operating different tools, different processing steps and final characterization for better understanding of what the course is about. The PMOS transistor has been chosen to be design and fabricate in the lab from beginning (wafer preparation) to the end (electrical measurement). 

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The first transistor was developed in 1947 as a low cost, low dimensional active component to replace vacuum tube bulbs. The first material was germanium and gradually transistors made by other semiconductors such as Silicon (Si) and Gallium Arsenide (GaAs).  The Si has gradually become the most dominant material in semiconductor industry since it is abundant element, cheap to produce, has good electrical properties and high quality silicon dioxide (SiO2) can be easily grown on it.   SiO2 has good dielectric properties and can act as oxide mask also can be selectively etched.

Transistors have huge applications; they are the main component on integrated circuits (IC). The PMOS is a type of transistor which based on Si with controlling oxidation. Figure 1 shows a schematic of simple PMOS.  

Figure 1: schematic of PMOS cross section

In each PMOS there are three main parts, gate that is deposited over insulator to control current, source that acts as supply to emit electron and drain to collect the emitted electron. The emitted electrons transport from source to drain through the channel. By changing the gate voltage, channel width is changing as well that results in a good control over source-drain current. Fabricate PMOS devices on Si wafers requires processing steps such as oxidation, lithography, implantation, and thermal processing, which will be discussed more in the following section. 

2. Theory


In this section, theoretical background about some of the methods and processing steps, which have been used in the Lab will be mention for better understanding what was done in the lab.

2.1. RCA Cleaning

Generally, every semiconductor fabrication begins with RCA cleaning which is a necessary approach to remove any kind of contaminations (organic, inorganic and metallic) from wafer’s surface. This technique, which first introduced by Radio Corporation of America Company has become a common technique in silicon semiconductor industry for decontamination. The RCA cleaning process starts with organic-cleaning, which is soaking the wafers in a solution of 5-parts of deionized water mixing with 1-part Ammonium Hydroxide and 1-part Hydrogen Peroxide at 75º C for 10 minutes. Then, wafers are rinsed in deionized water for 5 minutes. Next step is Buffered oxide etch (BOE) 1:50 for 30 seconds to eliminate any native surface oxide. Again wafers are rinsed in deionized water for 5 minutes followed by ionic-cleaning, which is soaking wafers in a solution of 6-parts of deionized water mixing with 1-part Hydrochloric Acid and 1-part Hydrogen Peroxide for 10 minutes at 75º C. At the end Rinse-Spin-Dry that is rinsing with deionized water for 5 minutes followed by spinner and dryer.

2.2. Sheet resistance

It is a common characterization technique, which provides information about resistivity, conductivity, doping and metal deposition thickness. Two different sheet resistance (Rs) measurement was performed in this work: Ordinary 4-Points Probe and CDE ResMap measurements.

2.3. 4-Points-Probe

In this method 4 tiny needles (probes) with same and small separation in-between make superficial contact with the surface of wafer. The principle operation of this method is to apply current between two of probes (which are most far from each other) and read the voltage between to other probes (wish are closest to each other), so from voltage drop Rs can be extracted. Figure 2 illustrates a schematic of this technique.



Figure 2: simple schematic of 4-point probe (Ossila)

Since the wafer’s thickness is smaller than the space between the probes (S), thin film equation for Rs was used in this work.


2.4. CDE Res Map


It is an effective and precise method based on 4-point probe theory to inspect and measure Rs all over the wafer. The tool was used in this work measures Rs of 81 different points all over the sample and provides a 2D map of average sheet resistivity for the measured wafer.

2.5. Oxidation


One of the main reasons about Si domination is silicon dioxide (SiO2). Growing an oxide layer is really important in microfabrication since oxide can act as dielectric, diffusion mask, insolation different devices, and ect. SiO2 can be easily grown on Si with high quality and can also selectively etch with good control over both growth and etch rate. In this work, SiO2 was used as gate dielectric and also diffusion mask in ion implantation for source and drain bombardment.

Steam oxide is an approach for growing an oxide on Si, which is usually performed in and furnace at temperature between 800-1200 (depends on fabrication design, thickness, quality and time). By introducing water vapor the chemical reaction stars and SiO2 will be formed. In this method Si will be consume, for 100 nm SiO2 thickness layer 44 nm Si will be consumed. The desirable layer thickness based on temperature and time can be calculated with Deal-Grove model.

Where (x0) is the oxide thickness, (B) and (B/A) is the parabolic reaction and linear reaction constant, respectively, and both depend on growth conditions. The () in Deal-Grove model is the time that needs to be considered for if there is any initial oxide. There is always an initial oxide but because in steam oxidation method growth rate is high and oxide growth fast on Si, () can be neglected in comparison to (t).

2.6. Ion-Implantation


Generally, there are two main methods to introduce dopants into the silicon: Thermal predisposition and Ion implantation. In thermal predisposition method small amount of dopants diffuse in to wafer by exposing wafer to desirable dopant gas in high temperature environment. Ion-implantation method is basically bombardment of wafer with desirable dopant spices. In this work ion-implantation was performed to define source and drain by bombardment of wafer with Boron as a dopant. Implantation was chosen rather than predisposition since it is much faster, less sensitive to surface contamination, excellent lateral profile and precise in terms of control over doping parameters such as dose and junction dept.

Figure 3 shows and schematic of ion-implantation mechanism. The device has six different essential components including: ion source, mass separator, acceleration column, beam focus, electrostatic scanning and the work chamber.  Ion species is provided from specific dopant source, afterward a needed specie will be selected trough and mass separator analyzer using magnetic field based on ion mass.


Figure 3: Ion implantation different segments. (Bodycote)

Required magnetic field for specific ion specie selection can be calculate from:

In which, m is the mass and n is charge of ion specie, and since ratio of m/n is unique for each species, needed one can be selected by applying a certain magnetic field.

Another important parameter in ion-implantation is time, in order to obtain certain amount of doping, wafers needs to be exposed for certain amount of time. This time can easily be calculated from:

In which, (Q) is the desired dose, (A) is the doping surface, (n) is the charge of the ion, (I) is the ion current area and (q) is the electron charge.

There are other parameters that needs to be considered in this method such as concentration peak Cp (how much is the maximum dopant concentration that injected to the substrate), projected range Rp (how deep the most of the dopant will go in to the substrate) and straggle ∆Rp (the maximum of diffusion parallel to ion beam). These elements can be extremely affect device’s performance and what they have been designed for.

In order to define a source and drain, selective surface area of wafer needs to be exposed to the beam, and rest must be protected by diffusion mask. As mentioned before SiO2 is a good chose since it can be easily grown on Si and can easily be etch to from a pattern for implantation. But a minimum thickness of SiO2 is required otherwise for thinner mask layer ion can be diffused trough and reach the Si surface. The minimum diffusion mask thickness is different for diffident masking materials and can be calculated:

Where Rp, ∆Rp, Cp are all mentioned before and Csub is the substrate dopant concentration.

2.7. Rapid Thermal Process (RTP)


Since the impanation is a physical process it can highly damage the substrate, RTP is required not only to heal the substrate lattice, but also to electrically activate dopant. RTP is a process to heat up Si wafers very fast for several seconds.

2.8. Groove and Stain technique


The junction depth (xj) is important parameters in microfabrication that means how deep dopant diffused into substrate. By rapid thermal process, dopant even more diffuse into the Si substrate.

Groove and Stain method is a simple fast method to measure the xj. In this method, a groove first is formed on substrate surface with a round rotation scrubber wheel with radius (R). Tiny droplet of stain solution place in the groove, which act as an electrolyte and makes a distinctive black/white color difference at n/p type region. A quick microscope inspection (a) and (b) as shown in figure 4 can be measured and used to calculate junction depth.

Figure 4: Groove and stain method

The junction depth in this method can be calculate below formula where a and b can be measured from microscope inspection and R is radius of grinding tool.

3. Experimental Procedure

In this section of report, procedure of oxidation, ion implantation, and RTP/furnace processing on control wafers are reported in detail. Diamond scriber was used to mark backside of wafers, otherwise it would not be possible to track all the sample. As mentioned before three different control wafers, C1, C2 and C3 were used to monitor different stage of fabrication procedure and to be used for some necessary measurements which are not possible to be done on device wafers. Next, 4-point probe and ResMap measurement were performed on the samples to measure wafer resistivity and make sure there is no abnormal difference between them. The data including average resistivity and standard deviation were collected, these data also were used as reference for checking upcoming processing. Afterward, RCA cleaning was done all the wafers to remove organic, inorganic and metallic contaminants from wafers.

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Certain oxide thickness was grown on top of all the wafers by thermal oxidation. Steam oxidation was preferred rather than dry oxide due to high growth rate. To grow 6500 Angstrom at 1100ºC, 62 minutes is needed, this value was calculated using online calculator website of University of Illinois. To make sure the required thickness will be achieved growth time was increased to 67 minutes. After thermal oxidation process, Spectramap and NanoSpec Spectrophotometer were used to measure grown oxide thickness.

Silicon Dioxide is a common diffusion mask layer in Si semiconductor industry. As mentioned before, a minimum oxide thickness is required to prevent dopant diffusion, which can be calculated. I order to experimentally investigate and figure out the minimum oxide thickness, the C1 wafer was step etched before ion impanation.  The C1wafres was gradually and step by step deep in BOH for 30 seconds for each step. Then the wafer was rinsed and dried. The final result was 12 steps with different oxide thickness on same wafer. Thickness of different steps, was measured and data was collected. Meanwhile oxide on C2, C3 wafers was completely removed, and all the wafers were loaded in implantation tool.

Gas 11B+ was chosen as dopant source gas for Boron implantation. Energy of 50 KeV and the current beam of 190 μA was selected to oblation a dose of 2e15 cm-3. After implantation wafers were tested by Tentype tool, in which to demonstrate the type and were still n-type. So C1 and C3 went under RTA process for dopant activation, while C2 wafer went through another activation technique and was used for steam oxidation at 1100º C to 3800 angstroms oxide on top of the C2 surface. Since resistivity is a function of doping concentration, measuring resistivity of different steps of C1wafres reveals that in which steps Boron was able to diffuse trough the oxide. In order to measure resistivity for each step half of the C1 wafer was completely etch for 4-point probe contact and the other half was kept as map to shows exactly the steps edges. ResMap measurement was done on C3 wafer. Oxide thickness on C2 was measured by spectrophotometer and microscope inspection was done. Once again, oxide was completely removed by BOH wet etching and C2 was prepared for ResMap and junction depth measurement. ResMap measurement was performed on both side of the C2 to observe the difference, followed by Groove and Stain measurement. In order to measure (a) and (b), C2 wafer was observed under microscope and junction depth was calculated based on (a+b) and (a-b) elements.

4. Result and Discussion

Figure 5 shows sample of ResMap measurement on C2 at the beginning of the process (without implantation). Average resistivity for C2 was 56.7 ohms/sq with standard deviation of 1 approximately, which indicate good uniformity all over the sample. Table 1 and its related plot (figure 6) shows the 4-point probe measurement result on C1 wafer after implantation. As oxide thickness decreasing from initial oxide thickness 6571 Å by roughly 600 Å in each etch-step, resistivity is unchanged at about 66 ohms/sq. Suddenly at oxide thickness of 3422 Å resistivity significantly increased to 1756 ohms/sq. This is a strong evidence that Boron dopant could diffuse trough the oxide and reach the wafer’s surface. Since the substrate is n-type, by introducing Boron to it, substrate’s surface has been changed to intrinsic Si with high resistivity.    

Figure 5: ResMap profile of C2 with no implantation

As oxide thickness gets thinner, more dopants can pass through and reach substrate’s surface and substrate begins to change from an intrinsic semiconductor to p-type semiconductor. By introducing more dopant resistivity decreases even less than unaffected area with 53 ohms/sq.

Figure 6: 4-point measurement result and related graph

Figure 7 shows the ResMap line-scan result of C1 wafer. Both two results had a good correlation except in some points, which can be attributed to the incorrect line-scan measurement. It has to be consider ion implantation profile is similar to Gaussian profile and there is always some diffusion even very small regardless of masking oxide thickness.

Figure 7: C1 ResMap Line-scan profile

Figure 8 illustrates ResMap measurement result of C3wafer after implantation and RTP profile. Average resistivity of 57 ohm/sq was obtained which was similar what was measured on C1 wafers without masking oxide. It has experimentally showed RTP activated the dopant and low resistivity was achieved due to electrically activation.  As mentioned before thermal processing is required after implantation.

Figure 8: C3 ResMsp profile after RTP

Figure 9 is ResMap profile result for C2 wafer with an average sheet resistivity of 113 ohm/sq which is an interesting result. It is worth to mention again that oxide was grown and etched on C2 wafer after implantation. This is a good demonstration of boron (with segregation coefficient of ~0.3) dopant tendency to diffuse into the oxide, due to the. Significant amount of dopant diffused into the oxide and subsequently removed by etching the oxide. The left dopant in the substrate was compensated by substrate dopant and net doping concentration decreased and resulted in higher sheet resistivity. 

Figure 9: C2 ResMsp profile after etching

Then junction depth measurement was performed on C2 with Groove and Stain method, the sample was inspected under microscope, figure 10. (a+b) equal 850.5 µm and (a-b) equal 94.5 µm was obtained from the microscope inspection picture and junction depth of 2.07 µm was calculated based on this values. 

Figure 10: Groove and Stain parameters 

5. Conclusion


In this work, some fundamental PMOS fabrication processes including oxide growth, ion implantation and thermal process that was performed in the lab was reported. This report was more about control wafers that were used for monitoring processing steps such as oxide thickness, sheet resistivity and junction depth. This kind of measurements are damaging the substrate surface so it was possible to perform on device wafers. Different control wafers for different measurement was mark and processed. C1 for implantation masking oxide, C2 for junction depth measurement and C3 for thermal processing were used and results were discussed in details. It was experimentally shown the minimum oxide thick to prevent dopant diffuse through oxide is approximately 400 nm. In addition, ion implantation followed by rapid thermal process affect was investigate which result in significant decrease in sheet resistivity. The junction depth measurement by Groove and Stain technique also performed with final result of roughly 2 µm.

Next lab report will cover more about device wafers and Athena simulation. 



1. S. Kurinec, Semiconductor Technology Overview & Microelectronics Fabrication Principles,  

Rochester Institute of Technology.

2. K. Hirschman, Lab course Lecture notes, Rochester Institute of Technology


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